Methods of making isolations including doped edge layer, for semiconductor-on-insulator substrates

ABSTRACT

Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation mask includes mask sidewalls. An implantation masking film is formed on the sidewalls of the patterned implantation mask. Ions are implanted into the semiconductor layer, using the patterned implantation layer and the implantation masking film as a mask, to thereby form a doped region in the semiconductor layer. Sidewall spacers are formed on the implantation masking film, opposite the patterned implantation mask. The doped region between the sidewall spacers is etched to thereby define a trench in the semiconductor layer between the sidewall spacers and a doped edge layer in the semiconductor layer which extends from the trench to the implantation masking film. Insulating material is then formed in the trench.

FIELD OF THE INVENTION

This invention relates to semiconductor fabrication methods, and moreparticularly to methods of manufacturing semiconductor-on-insulatorsubstrates.

BACKGROUND OF THE INVENTION

Semiconductor-on-insulator (SOI) substrates, also referred to assilicon-on-insulator substrates, are being used to fabricatemicroelectronic devices with a high integration density. As is wellknown to those having skill in the art, semiconductor-on-insulatorsubstrates may be contrasted from bulk semiconductor substrates. In bulksemiconductor substrates, the active devices such as transistors areformed in the bulk semiconductor substrate. In contrast, insemiconductor-on-insulator substrates, active devices such astransistors are formed in a semiconductor layer which is separated froma substrate by a buried insulating layer.

In semiconductor-on-insulator substrates, it is important to isolate theactive devices from one another. A common technique for device isolationis local oxidation of silicon, often referred to as LOCOS.Unfortunately, as the size of the active semiconductor devices isreduced to below submicron size, the LOCOS technique may be difficult toimplement.

Another conventional isolation technique is a trench isolationtechnique, wherein a trench is formed in a semiconductor layer and thenfilled with an insulating material. Trench isolation techniques arecapable of producing planarized surfaces, with good insulationcharacteristics.

The LOCOS technique may be especially inappropriate forsemiconductor-on-insulator substrates. Accordingly, trench isolationtechniques are especially useful for silicon-on-insulator substrates.

It is also known that an edge of an active device region, which isadjacent the device isolation region, may become inverted because ofsurface charges (charges between the active region and the deviceisolation region) and fixed charges within the device isolation region(sidewall inversion). Moreover, the leakage current in an active devicesuch as a transistor may be increased by a parasitic transistor whichmay be formed in the edge of the active region. This is known as theedge transistor effect. In order to overcome these and other problems,it has been proposed to form a doped edge layer in the device isolationregion, wherein the edge of the device isolating region is doped withdopants of the same conductivity type as the substrate active region, tothereby increase the doping concentration at the edge.

FIG. 1 is a cross-sectional view of a semiconductor-on-insulatorsubstrate including a doped edge layer. The doped edge layer increasesthe doping concentration at the edge of the device isolation region.

As shown in FIG. 1, the semiconductor-oninsulator substrate includes abulk substrate 100, a buried insulating layer 10 and a semiconductorlayer 20 which forms the active device layer. A pad oxide film 30 and apatterned implantation mask 40 are included on the semiconductor layer20. The semiconductor layer 20 is etched using the pad oxide 30 and thepatterned implantation mask 40 as masks, to thereby form a trench 1.Ions 23 are implanted at an angle, into the sidewall of trench 1, tothereby form a doped edge layer 5 at the edge of the active region, onthe sidewall of the trench 1. The doped edge layer 5 preferably has thesame conductivity type as the semiconductor layer 20, and reduces orprevents sidewall inversion and edge transistor effects.

Unfortunately, as shown in FIG. 1, when the ions 23 are implanted at anangle, the pad oxide film 30 and the patterned implantation mask 40 mayprevent implantation of ions 23 into the portion A at the interfacebetween the pad oxide film 30 and the semiconductor layer 20. In orderto completely implant ions into portion A, the implantation energy maybe increased. Unfortunately, this may result in overimplantation in theremaining portions, so that the doped edge layer expands into the activeregion of the semiconductor layer. This may reduce the area of theactive region and may reduce device integration density.

FIGS. 2A-2C illustrate another method which can form a device isolationregion without overimplantation into the active semiconductor layer. Asshown in FIG. 2A, a pad oxide layer 30 is formed on semiconductor layer20. A patterned implantation mask 40 is formed on pad oxide film 30.Ions 50 are implanted into the semiconductor layer 20 using thepatterned implantation mask 40 as a mask, thereby forming doped region52. Thermal treatment is then performed so that the dopants in dopedregion 52 diffuse laterally, thereby forming a doped edge layer 54.

Then, referring to FIG. 2B, the semiconductor layer 20 is etched usingthe patterned implantation mask 40 as a mask, to form a trench 1. Aninsulating material is filled in the trench 1 to form a device isolatingregion 100 of FIG. 2C.

Accordingly, as shown in FIGS. 2A-2C, doped edge layer 5 can preventsidewall inversion and edge transistor effects. Moreover, the doped edgelayer 54 can be uniformly doped across the thickness thereof.Unfortunately, since the doped edge layer 54 is formed by diffusingdopants from the doped region 52, it may be difficult to control thedoping concentration and lateral doping profile in doped edge layer 54.

It is known to solve these problems by using a method shown in FIGS.3A-3D. Referring to FIG. 3A, a doped region 52 is formed as was alreadydescribed in connection with FIG. 2A. Then, referring to FIG. 3B, anoxide film is formed, preferably by chemical vapor deposition (CVD) onthe pad oxide layer 30 and on the patterned implantation mask 40. Theoxide layer is then anisotropically etched to form sidewall spacers 60on the sidewall of the patterned implantation mask 40, as shown in FIG.3B. As shown in FIG. 3C, the pad oxide layer 30 and semiconductor layer20 are etched, using the patterned implantation mask 40 and sidewallspacers 60 as a mask, to thereby form a trench and a doped edge layer56. As shown in FIG. 3D, the trench is filled with an insulatingmaterial, to thereby form device isolation region 110.

Referring again to FIGS. 3A-3C, W1 indicates the width of the deviceisolation region which is initially defined. T4 indicates the width ofthe sidewall spacer 60. T5 indicates the width of the device isolationregion which is finally defined. Accordingly, the width T5 of the deviceisolation region is obtained by subtracting the width T4 of the spacer60 from the width W1 of the isolation region which is initially defined.

In the embodiment of FIGS. 3A-3D, the spacer 60 is formed on thesidewall of the patterned implantation mask 40 and is then used as amask in etching the semiconductor layer 20, except for the doped edgelayer 52. Thus, the width of the device isolating region 110 is reducedby twice the width T4 of the spacer 60. Moreover, since the doped edgelayer 56 is not formed by diffusion, the doping concentration andprofile in the doped edge layer can be controlled by controlling thedoping concentration in doped region 52.

Notwithstanding the above-described improvements in device isolationmethods, there continues to be a need to device isolation methods whichcan control the doping concentration and profile in doped edge layerswhile reducing the thickness of the doped edge layer, so that the activeregions in the semiconductor layer can be enlarged.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide improvedmethods for fabricating isolation regions for semiconductor layers ofsemiconductor-on-insulator substrates.

It is another object of the present invention to provide deviceisolation region fabrication methods for semiconductor-on-insulatorsubstrates which can control the doping concentration and doping profilein doped edge layers.

It is another object of the invention to provide isolation regionfabrication methods for semiconductor-on-insulator substrates which canreduce the thickness of the edge impurity layer, to thereby enlarge theactive device regions in the semiconductor layer.

These and other objects are provided, according to the presentinvention, by using an implantation masking film on the sidewalls of apatterned implantation mask, to reduce the thickness of a doped edgelayer and thereby allow an increase in the size of the active deviceregions. The doped edge layer is formed by implantation, so that thedoping concentration and profile can be well controlled.

In particular, methods of fabricating isolation regions forsemiconductor layers of semiconductor-on-insulator substrates accordingto the present invention, form a patterned implantation mask on thesemiconductor layer. The patterned implantation mask includes masksidewalls. An implantation masking film is formed on the sidewalls ofthe patterned implantation mask. Ions are implanted into thesemiconductor layer, using the patterned implantation layer and theimplantation masking film as a mask, to thereby form a doped region inthe semiconductor layer. Sidewall spacers are formed on the implantationmasking film, opposite the patterned implantation mask. The doped regionbetween the sidewall spacers is etched, to thereby define a trench inthe semiconductor layer between the sidewall spacers, and a doped edgelayer in the semiconductor layer which extends from the trench to theimplantation masking film. Insulating material is then formed in thetrench.

In embodiments of the present invention, a pad oxide film is formed onthe semiconductor layer of a semiconductor-on-insulator substrate. Apatterned implantation mask is formed on the pad oxide film. Thepatterned implantation mask includes mask sidewalls. An implantationmasking film is formed on the patterned implantation mask opposite thesemiconductor layer, on the sidewalls of the patterned implantation maskand on the pad oxide film between the sidewalls. Ions are implanted intothe semiconductor layer, using the patterned implantation layer and theimplantation masking film on the sidewalls of the patterned implantationmask as a mask, to thereby form a doped region in the semiconductorlayer. A spacer layer is formed on the patterned implantation maskopposite the semiconductor layer, on the sidewalls of the patternedimplantation mask and on the pad oxide film between the sidewalls. Thespacer layer is anisotropically etched to produce sidewall spacers onthe implantation masking film, opposite the patterned implantation mask.The doped region is then etched between the sidewall spacers, to therebydefine a trench in the semiconductor layer between the sidewall spacers,and a doped edge layer in the semiconductor layer which extends from thetrench to the implantation masking film. The trench is then filled withinsulating material.

The trench may be filled with insulating material by forming aninsulating material layer filling the trench and on the patternedimplantation mask opposite the semiconductor layer. The insulatingmaterial layer is then etched to expose the patterned implantation mask.The patterned implantation mask is then removed. The patternedimplantation mask may be removed by chemical mechanical polishing theinsulating material layer to expose the patterned implantation mask.

The implantation masking film may be formed of silicon nitride and thepatterned implantation mask may be formed with chemical vapor depositedsilicon dioxide. Before filling the trench with insulating material, aprotective oxide may be formed on the trench sidewalls.

Isolation region forming methods according to the present invention canform reduced thickness doped layers, so that the area for the activeregion in the semiconductor layer can be enlarged. Moreover, because thedoped edge layer is formed by implantation into a doped region, thedoping density and profile may be well controlled. Improved trenchisolated semiconductor-on-insulator devices are thereby provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional trench isolatedsemiconductor-on-insulator device.

FIGS. 2A-2C are cross-sectional views of a conventional method offabricating an isolation region for a semiconductor layer of asemiconductor-oninsulator substrate.

FIGS. 3A-3D are cross-sectional views of another conventional method offabricating an isolation region for a semiconductor layer of asemiconductor-oninsulator substrate.

FIGS. 4A-4F are cross-sectional views of methods of fabricatingisolation regions for semiconductor layers of semiconductor-on-insulatorsubstrates according to the present invention, during intermediatefabrication steps.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout. Moreover, eachembodiment described and illustrated herein includes its complementaryconductivity embodiment as well. It will also be understood that when alayer is referred to as being "on" another layer, it can be directly onthe other layer, or intervening layers may also be present.

FIGS. 4A-4F are cross-sectional illustrations of methods of fabricatingisolation regions for semiconductor layers of semiconductor-on-insulatorsubstrates according to the present invention. Referring now to FIG. 4A,a patterned implantation mask 40 is formed on a pad oxide film. Inparticular, a semiconductor-on-insulator substrate is provided having abulk substrate 100, a buried insulating layer 10 on the bulk substrate100 and a semiconductor layer 20 on the buried insulating layer 10. Padoxide film 30 may be formed by thermally oxidizing the semiconductorlayer 20. Patterned implantation mask 40 may be formed by depositing amaterial such as silicon nitride on the pad oxide 30 and then patterningthe silicon nitride to form patterned implantation mask 40.

Patterned implantation mask 40 is preferably formed of a material whichhas an etch selectivity which is different from that of the pad oxidematerial for a given etching process. For example, silicon nitride ispreferably used for the patterned implantation mask 40 and silicondioxide is preferably used for the pad oxide film 30. As shown in FIG.4A, W2 indicates the width of the device isolation region which isinitially defined.

Referring now to FIG. 4B, an implantation masking film 62 is formed onthe patterned implantation mask 40 opposite the semiconductor layer 20,on the sidewalls of the patterned implantation mask and on the pad oxidefilm 30 between the sidewalls. The implantation masking film 62 may beformed by chemical vapor deposition (CVD) of silicon dioxide on thesubstrate. As also shown in FIG. 4B, a doped region 52 in semiconductorlayer 20 is formed by implanting ions 50 using the patternedimplantation mask 40 and the implantation masking film 62 as a mask.

Still referring to FIG. 4B, the thickness of the implantation maskingfilm is indicated as Ti. Since the width W3 of the doped region 52 issmaller than the width W4 of FIG. 3A by an amount which is equal totwice T1, the active region side is enlarged by twice T1. It will beunderstood that the conductivity type of the dopants 50 which areimplanted to form doped region 52 is preferably the same as theconductivity type of the semiconductor layer 20.

Referring now to FIG. 4C, sidewall spacers 64 are formed on theimplantation masking film 62 opposite the patterned implantation mask40. In particular, a spacer layer such as a silicon dioxide spacerlayer, is blanket deposited using chemical vapor deposition. The spacerlayer is formed on the patterned implantation mask 40 opposite thesemiconductor layer 20, on the sidewalls of the patterned implantationmask and on the pad oxide film between the sidewalls. More specifically,when the implantation masking film 62 has been blanket deposited on thesubstrate, the spacer layer is formed on the implantation masking filmwhich is on the patterned implantation mask opposite the semiconductorlayer, on the implantation masking film which is on the sidewalls of thepatterned implantation mask and on the implantation masking film whichis on the pad oxide film between the sidewalls.

The spacer layer is then anisotropically etched to form the sidewallspacers 64. The implantation masking film 62 on the patternedimplantation mask 40 opposite substrate 20 and on the pad oxide layer 30opposite the doped region 52 is also removed during the anisotropicetching process.

Still referring to FIG. 4C, T3 denotes the width between the sidewallspacers. When the value obtained by adding the width of the spacers 64to that of the thickness of implantation masking film 62 is the same asthe width T4 of the spacers 60 of FIG. 3C, then the width T3 is the sameas the width T5 of FIG. 3C. However, when the width of the spacer 64 ofFIG. 4C is the same as the width T4 of the spacer 60 of FIG. 3C, T3 isless than T5 of FIG. 3C. Thus, the width T3 of the device isolationregion which is produced by the present invention can be narrower thanthe width T5 of the device isolation region which is produced byconventional methods.

Referring now to FIG. 4D, doped edge layer 58 is formed by etching thedoped region 52 between the sidewall spacers 64, to thereby define atrench 1 in the semiconductor layer 20 between the sidewall spacers 64and to also define a doped edge layer 58 in the semiconductor layerwhich extends from the trench 1 to the implantation masking film 62 onthe sidewall of patterned implantation mask 40. The sidewall spacers 64are used as a mask. The buried insulating layer 10 acts as an etch stop.

As shown in FIG. 4D, the width T2 of the doped edge layer 58 is the sameas the width of the spacer 64. Moreover, since the doped edge layer 58according to the present invention is reduced in width by the thicknessof the implantation masking film 62 on the sidewall of the patternedimplantation mask 40, the width of the active region may be enlarged bytwice the thickness of the implantation masking film 62.

Referring now to FIG. 4E, the trench is filled with insulation material120a. An insulating material layer is preferably formed, filling thetrench and on the patterned implantation mask opposite the semiconductorlayer. The insulating material layer is then etched to expose thepatterned implantation mask 40, for example using chemical mechanicalpolishing (CMP).

In an alternate embodiment of the present invention, a thin oxide film,not illustrated in FIG. 4E, may be formed on the sidewalls of the trench1 of FIG. 4D prior to forming the insulating material layer. The thinoxide film may be formed to remove the damage in the semiconductor layer20 which results from the etch process which forms trench 1 of FIG. 4D.

Finally, as shown in FIG. 4F, the patterned implantation mask 40 isremoved and the pad oxide film 30 is also removed. Phosphoric acid maybe used to etch the patterned implantation mask 40 and a buffered oxideetch (BOE) may be used to etch the pad oxide film 30.

A comparison between the isolation regions which are formed according tothe present invention (FIGS. 4A-4F) and those which are conventionallyformed (FIGS. 3A-3D) will now be provided. If the width T4 of the spacer60 of FIG. 3C is the same as the sum of the widths of the spacer 64 andthe implantation masking film 62 of FIG. 4C, the width T3 of the deviceisolation region would be the same as the width TS in FIG. 3C. Thus, thewidth T2 of the doped edge layer 58 according to the present inventionbecomes narrower than the width T4 in FIG. 3C by the width T1 of theimplantation masking film 62. Moreover, if the width of the spacer 64 ofFIG. 3C is the same as the width T4 of the spacer 60 in FIG. 3C, thewidth of the doped edge layer 58 of FIG. 4C becomes the same as that ofthe doped edge layer 56 of FIG. 3C. Thus, the width T3 of the deviceisolation region is narrower than the width T5 of FIG. 3C. In bothcases, the active region of the semiconductor layer 2 is enlarged by anamount which is equal to twice the width of the implantation maskingfilm 62, compared to that of the conventional method of FIGS. 3A-3D.

Accordingly, the present invention allows the thickness of the dopededge layer to be reduced. Moreover, the area of the device isolationregion can be reduced. The area of the active region can also beenlarged.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

That which is claimed:
 1. A method of fabricating an isolation regionfor a semiconductor layer of a semiconductor-on-insulator substrate,comprising the steps of:forming an implantation mask on thesemiconductor layer, the implantation mask having mask sidewalls;forming an implantation masking film on the sidewalls of theimplantation mask, to thereby define an opening between the implantationmasking film on the sidewalls of the implantation mask; implanting ionsinto the semiconductor layer, through the opening, to thereby form adoped region in the semiconductor layer; forming sidewall spacers on theimplantation masking film, opposite the patterned implantation mask;etching a part of the doped region between the sidewall spacers tothereby define a trench in the semiconductor layer between the sidewallspacers, and a doped edge layer in the semiconductor layer which extendsfrom the trench to the implantation masking film; and forming insulatingmaterial in the trench.
 2. A method according to claim 1 wherein thestep of forming an implantation mask on the semiconductor layer ispreceded by the step of:forming a pad oxide film on the semiconductorlayer; and wherein the step of forming an implantation mask comprisesthe step of: forming an implantation mask on the pad oxide film, theimplantation mask including mask sidewalls.
 3. A method according toclaim 1 wherein the step of forming an implantation masking filmcomprises the step of:forming an implantation masking film on theimplantation mask opposite the semiconductor layer, on the sidewalls ofthe implantation mask and on the semiconductor layer between thesidewalls.
 4. A method according to claim 1 wherein the step of formingsidewall spacers comprises the steps of:forming a spacer layer on theimplantation mask opposite the semiconductor layer, on the sidewalls ofthe implantation mask and on the semiconductor layer between thesidewalls; and anisotropically etching the spacer layer to produce thesidewall spacers on the implantation masking film, opposite theimplantation mask.
 5. A method according to claim 1 wherein the step offorming insulating material in the trench comprises the step of:fillingthe trench with insulating material.
 6. A method according to claim 5wherein the step of filling the trench with insulating materialcomprises the steps of:forming an insulating material layer filling thetrench and on the implantation mask opposite the semiconductor layer;etching the insulating material layer to expose the implantation mask;and removing the implantation mask.
 7. A method according to claim 6wherein the removing step comprises the step of:chemical mechanicalpolishing the insulating material layer to expose the implantation mask.8. A method of fabricating an isolation region for a semiconductor layerof a semiconductor-on-insulator substrate, comprising the stepsof:forming a pad oxide film on the semiconductor layer; forming animplantation mask on the pad oxide film, the implantation mask havingmask sidewalls; forming an implantation masking film on the implantationmask opposite the semiconductor layer, on the sidewalls of theimplantation mask and on the pad oxide film between the sidewalls, todefine an opening between the implantation masking film on the sidewallsof the implantation mask; implanting ions into the semiconductor layer,through the opening, to thereby form a doped region in the semiconductorlayer; forming a spacer layer on the implantation mask opposite thesemiconductor layer, on the sidewalls of the implantation mask and onthe pad oxide film between the sidewalls; anisotropically etching thespacer layer to produce sidewall spacers on the implantation maskingfilm, opposite the implantation mask; etching a part of the doped regionbetween the sidewall spacers to thereby define a trench in thesemiconductor layer between the sidewall spacers, and a doped edge layerin the semiconductor layer which extends from the trench to theimplantation masking film; and filling the trench with insulatingmaterial.
 9. A method according to claim 5 wherein the step of fillingthe trench with insulating material comprises the steps of:forming aninsulating material layer filling the trench and on the implantationmask opposite the semiconductor layer; etching the insulating materiallayer to expose the implantation mask; and removing the implantationmask.
 10. A method according to claim 9 wherein the removing stepcomprises the step of:chemical mechanical polishing the insulatingmaterial layer to expose the implantation mask.
 11. A method accordingto claim 8 wherein the implantation masking film is formed of siliconnitride.
 12. A method according to claim 8 wherein the implantation maskis formed of chemical vapor deposited oxide.
 13. A method according toclaim 8 wherein the etching step is followed by the step of:forming anoxide on the trench sidewalls.
 14. A method according to claim 8 whereinthe step of forming a spacer layer comprises the step of:forming aspacer layer on the implantation masking film which is on theimplantation mask opposite the semiconductor layer, on the implantationmasking film which is on the sidewalls of the implantation mask and onthe implantation masking film which is on the pad oxide film between thesidewalls.